1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a drop-in test structure fabricated upon a production integrated circuit elevational profile for characterizing an integrated circuit process.
2. Description of the Related Art
Fabrication of integrated circuits requires that precisely controlled quantities of impurities be introduced into small regions of a semiconductive substrate and that these regions be interconnected to create microelectronic components and integrated circuits. The patterns used to define such regions and interconnections are created using lithographic processes. To form the patterns, layers of photoresist material are applied as thin films to the upper surfaces of the substrate or to elevational profiles successively built upon the substrate. The photoresist is selectively exposed to a form of radiation such as specific optical wavelengths, ultraviolet light (xe2x80x9cUV lightxe2x80x9d), X rays, or electrons. An exposure tool and mask are used to effect the exposure to UV light or X rays, while a data tape is used in electron beam lithography.
The exposure mask includes clear and opaque regions that define the features to be patterned in the photoresist. Areas of the photoresist exposed to radiation may be rendered preferentially soluble or insoluble, relative to unexposed photoresist, in a developing solvent. The change in solubility depends upon the type of photoresist used. Following development of the photoresist, the patterned photoresist is used as a mask during removal of exposed portions of the underlying substrate or conductive materials such as polycrystalline silicon or metal. As such, the pattern is transferred from the exposure mask to the integrated circuit topography. Similar lithography techniques are used to pattern photoresist above portions of the substrate and conductive features (e.g., gate conductors) to selectively block ion implantation when impurities are introduced into the substrate (e.g., during source and drain formation).
Projection printing is the predominant method used for optically transferring a pattern from an exposure mask to a photoresist-coated wafer. In projection printing, wafers are separated from the masks by large distances. Lens elements or mirrors are used to focus the mask image onto the photoresist. Current projection printing systems use refractive optics to project the mask image onto the photoresist. Because it is impractical to build a refractive lens capable of projecting an image across an entire wafer, refractive systems project the image across a portion of the wafer. The projection field is then moved across the wafer using a xe2x80x9cstep-and-repeatxe2x80x9d procedure. Masks used with step-and-repeat aligners are commonly referred to as xe2x80x9creticlesxe2x80x9d to distinguish them from masks that project images across an entire wafer.
The manufacture of semiconductor integrated circuits involves a loss of chip yield due to the presence of various defects. The two basic types of defects that may occur when conductive layers are formed on an integrated circuit are extra material defects (xe2x80x9cEMDxe2x80x9d) and missing material defects (xe2x80x9cMMDxe2x80x9d). EMD may occur when the conductive structures include material extending beyond predefined boundaries. Such material may extend to another conductive structure, causing a xe2x80x9cshortxe2x80x9d to be formed between the two conductive structures. MMD may occur when a gap is formed in a conductive structure. Such a defect may cause the formation of an xe2x80x9copenxe2x80x9d conductive structure in which the continuity of the conductive structure is broken.
Defects that occur in a regular or repeating pattern typically result from shortcomings in the processing methodology, such as misalignment of a reticle or tilt of the wafer. These defects are known as systematic defects. In contrast, random defects occur without a pattern. Both EMD and MMD may be either systematic or random defects. For example, systematic problems in step coverage across areas of large elevational disparity may lead to the formation of open circuits due to missing material at the step. As another example, short circuits may be formed due to random distribution of particulate matter upon the die (which may result in connections between adjacent conductive lines) or upon the reticle used to pattern the die (which may result in conductive material between adjacent lines being retained rather than removed due to undesired masking by the particulate matter).
In order to detect defects that arise during fabrication of integrated circuits, test structures may be formed upon designated sites on a semiconductor wafer. Formation of the test structures may include multiple processing steps different from processes used to form production integrated circuits. For example, different reticles may be used to pattern successive layers of the test structures than are used to pattern the production die. As such, the elevational profile of a test structure that includes multiple layers of patterned conductive material may differ from the elevational profile of neighboring integrated circuits. Consequently, such test structures may not give an accurate indication of systematic problems that may occur due to elevational disparity in the production integrated circuit or random problems that occur in a production setting.
Alternatively, a small area within a production die may be reserved for a test device or devices. Test devices so formed may avoid the problems associated with using non-production reticles for successive layers of the test elevational profile. Forming test structures as part of a production die, however, significantly reduces the area available for the test structures. As such, random defects occurring with low frequency might not be detected.
The problems outlined above may be solved by the technique hereof for forming and using a test structure for characterizing a production integrated circuit fabrication methodology (xe2x80x9cproduction methodologyxe2x80x9d) and a production integrated circuit topography (xe2x80x9cproduction topographyxe2x80x9d) formed using the production methodology. As used in this application, xe2x80x9cproduction integrated circuit topographyxe2x80x9d describes a topography that is contained within a packaged integrated circuit intended for use by a consumer of a product including the integrated circuit as an integral component. That is, a production topography is descriptive of an integrated circuit die that has been scribed, separated from a wafer, tested, packaged, and shipped. xe2x80x9cProduction integrated circuit fabrication methodologyxe2x80x9d describes a process for fabricating a production integrated circuit topography.
A production integrated circuit elevational profile (xe2x80x9cproduction elevational profilexe2x80x9d or xe2x80x9cproduction profilexe2x80x9d) as used in this application refers to a set of sequentially formed elevational features encompassing a subset of a production topography. That is, a production profile is formed according to a subset of the sequence of steps constituting the production methodology, whereas as a production topography is formed according to a complete production methodology sequence. More specifically, a production profile is formed according to processing steps that occur prior to dicing the wafer (i.e., separating a complete wafer into individual chips or die). As such, a production profile is distinguishable from an elevational profile intended strictly to be used for testing purposes and not intended to function in whole or in part as an operable component of an electronic device.
A production topography is considered to be elevationally complete prior to scribing and separation of the die from the wafer. As such, a production profile may represent either a substantially elevationally complete production topography or a partially complete production topography. That is, according to an embodiment, a production elevational profile may be formed by a majority of steps used to produce the integrated circuit. According to an alternative embodiment, a production elevational profile may be formed by a minority of steps used to produce the integrated circuit. The production profile includes both features that determine elevational disparity of the production topography (such as conductive lines) and features that do not impact upon elevational disparity (such as source and drain impurity distributions).
The production methodology may include using a step-and-repeat process of patterning successively deposited conductive layers. A test reticle having a test pattern thereon may be substituted for a production reticle and used to pattern the test structure upon select die of the wafer. Preferably, the test structure occupies substantially an entire chip or die when patterned, so that the test structure may be used to detect random events occurring with low frequency. According to an embodiment, the test structure may be patterned upon a substantially complete production elevational profile (i.e., an elevational profile that has undergone a majority of the production methodology). According to an alternate embodiment, the test structure may be patterned upon an upper surface of a partially completed production elevational profile (i.e., an elevational profile that has undergone a minority of the production methodology). That is, the test structure may be patterned upon an elevational profile that is not itself a complete topography but that is capable of functioning as part of an integrated circuit if processing is completed.
According to an embodiment, a test reticle may be used to pattern select chip sites upon a wafer. The select chip sites may include sites previously selected to receive test structures as part of routine monitoring of the fabrication process. For example, test structures may be formed upon several pre-selected sites of a single wafer on, e.g., a daily or weekly basis to ensure that the resulting product chips meet design criteria. Alternatively, the select sites may be patterned with the test reticle rather than a production reticle in response to problems discovered during testing of finished production wafers. For example, electrical testing of finished wafers may reveal defects in the chips. As such, the test reticle may be used to pattern test structures upon selected chip sites of wafers at various stages of production to isolate critical processing steps at which the defects are introduced. In this embodiment, the selected chip sites are sites that otherwise would have been used for fabricating production integrated circuit topographies (i.e., the selected sites are not previously dedicated test sites). Further action may then be taken to identify the processing conditions or equipment responsible for the defects and to effect repairs or changes necessary to produce usable product. Test structures may be formed with an increased frequency (e.g., upon one or more wafers in each batch loaded into the process to be corrected) until the problem is resolved.
According to a further alternative, test structures may be formed across an entire wafer to enable identification of intra-wafer variations in processing. For example, formation of test structures across an entire wafer may reveal a regular pattern of defects across the wafer attributable to systematic errors in processing. Forming test structures across an entire wafer may also reveal that processing conditions vary between the center of the wafer and the edges such that functioning integrated circuits will be produced only in certain regions of the wafer rather than across the entire wafer. According to this embodiment, the test structures may be formed either on substantially complete or on partially complete production elevational profiles.
The test structure may include alternating grounded and floating conductive lines. Floating conductive lines are defined to be lines that are neither grounded nor powered during the optical testing of the test structure. Stimuli may be applied to the test structure in order to detect the presence of defects in the test structures. According to an embodiment, the stimuli may be electrons applied by an electron microscope. The wafer upon which the test structure is formed may be placed in a scanning electron microscope (xe2x80x9cSEMxe2x80x9d) and irradiated with electrons. The test structure preferably allows for a rapid optical inspection to determine if defects are present.
When the test structure is irradiated with electrons (that is, during xe2x80x9cvoltage contrast inspectionxe2x80x9d), conductive lines that are floating will emit more electrons than grounded conductors will. This occurs because the grounded conductors absorb a portion of the electrons directed toward them, thus emitting fewer electrons than the floating conductive lines. If a defect is present that causes a short between a grounded and an ungrounded line, the two lines will emit about the same quantity of electrons. During a scan of the test structure, the lines may appear as an alternating series of bright (i.e., reflecting more electrons) and darkened (i.e., reflecting fewer electrons) conductive lines. If a defect is present in the test structure, this condition may be detected by scanning the test structure while the structure is being irradiated with electrons. If a floating and grounded line are shorted to each other, a portion of the floating line in the vicinity of the defect will appear to be darkened, thus readily signaling, by inspection scan, the presence of a defect.
An advantage of this test structure and testing method is that the presence and location of the defect may be readily determined. If a short occurs between a floating and a grounded line, the floating line will appear darkened in the vicinity of the short. Thus, when the region in which the defect is present is scanned, a change in the electronemitting appearance of a conductive line will occur. Without being bound by theory, it is thought that, due to the resistivity of the conductive lines, most low-power electrons striking the floating line will be emitted before they can travel to the extra material and then to ground. The proportion of electrons able to travel to ground is thought to increase with increasing proximity to the short. Thus, this method allows not only the detection of extra material defects, but also allows a rapid method of determining the location of the defect. This avoids scanning the entire test structure. Voltage contrast inspection allows a much coarser scan since a much larger area of the test structure will appear altered due to the presence of a defect.
Missing material defects in the grounded conductive line may also be found using a voltage contrast detection method. If a defect is present on a conductive line that is grounded, such that the continuity of the conductive line is broken, a portion of the conductive line will now be floating. During inspection, while the test structure is irradiated with electrons, the floating portion of the conductive line will glow, while the grounded portion of the conductive line will be darkened. By scanning a portion of the test structure near the point of grounding, and a portion of the test structure farther away from the point of grounding, an open in a grounded conductive line may be detected. The scanned portions may represent only a fraction of the total area of the test structure. This offers an advantage over conventional optical inspections, which may require scanning the entire test structure to determine the presence of opens in a conductive line. By minimizing the area required for scanning, the test structure may be used to quickly validate a process step involving the formation of conductive features.
In an embodiment, the test structure includes at least two conductive lines. The first conductive line is preferably coupled to ground. The second conductive line is preferably floating. The lines are formed on the upper surface of a production integrated circuit elevational profile. A transistor may be coupled to the first conductive line such that the transistor couples the first conductive line to the ground. The transistor is preferably a depletion-mode transistor. When a voltage is applied to the transistor, the transistor is configured to disconnect the first conductive line from the ground, thus rendering the first conductive line floating. The transistor may be coupled to a pad. The pad is preferably configured such that a voltage applied to the pad causes the transistor to disconnect the first conductive line from ground. An advantage of placing a transistor between the conductive line and the ground is that the line can be switched from a grounded to floating state. This allows the test structure to be used for a variety of testing techniques, including non-grounded electrical testing. Examples of test methods with which the above described test structure may be used include, but are not limited to, voltage contrast inspectability, basic particle size distribution, grounded electrical testing, and non-grounded electrical testing.
When compared to optical testing (such as basic particle side distribution testing), voltage contrast inspection and electrical testing have the advantage of allowing detection of very small defects and/or defects having low contrast with the background. As such, voltage contrast inspection and electrical testing provide increased signal-to-noise discrimination. Voltage contrast inspection has the further advantage of proceeding rapidly, such that test results may be obtained in a matter of hours. By way of comparison, several days may pass before electrical testing results are available. The ability to obtain results rapidly, thus minimizing manufacturing down time and/or production of defective materials during testing, is of great economic benefit to integrated circuit fabricators.
The first conductive line is preferably formed in a comb-like structure. The first conductive line preferably includes a main body portion with projections extending from the main body portion. The second conductive line is preferably routed in a serpentine fashion around the projections of the first conductive line. The second conductive line may be positioned such that a distance between the first and second conductive lines is constant.
The test structure may also include additional conductive lines. A third conductive line coupled to ground and a fourth floating line may also be incorporated into the test structure. The third line is preferably coupled to ground through a transistor. The transistor is preferably a depletion-mode transistor. When a voltage is applied to the transistor, the transistor is configured to disconnect the third conductive line from ground, thus rendering the third conductive line floating.
When four conductive lines are incorporated into the test structure, two of the lines, preferably the first and the fourth conductive lines, are comb-like lines. Both the first and fourth lines include projections extending out from a main portion of the conductive lines. The projections extend toward and away from the opposing conductive line. Sandwiched between the comb-like first and fourth lines, the second and third conductive lines are routed in serpentine fashion between the projections of the first and fourth lines. Preferably the spacing between all of the lines is substantially constant such that at any given point the distance between neighboring lines is substantially the same. The use of comb-like and serpentine lines allows a greater surface area of the integrated circuit elevational profile to be covered while maintaining a minimal number of conductive lines. The use of comb-like and serpentine lines also improves discriminating between open and shorting defect mechanisms.
The width of the individual conductive lines may be varied to allow testing of the production of wide conductive lines coupled to narrow conductive lines on the integrated circuit elevational profile. Alternatively, the conductive lines may be formed such that all of the conductive lines have substantially the same width and a constant spacing between the conductive lines. By forming conductive lines having the same width and spacing, the test structure may be used for particle size testing, as well as defect detection. The conductive lines are preferably formed from a conductive material during the formation of conductive features on other parts of the integrated circuit elevational profile. Examples of conductive materials include, but are not limited to, conductive metals (such as aluminum, titanium, and cobalt) and silicided polysilicon.
In another embodiment, the stimuli applied to the test structure may be electrons from an electrical tester. Test pads may be incorporated into the test structure. When defects are detected in a test structure using an inspection, as described above, the presence of defects may be electrically verified. By incorporating test pads into the structure, the presence of extra material defects and missing material defects may be detected electrically. The test pads are attached to each of the conductive lines to allow electrical testing of the conductive lines. The test pads are preferably connected to the conductive lines to allow testing of shorts between the lines and to find opens in the conductive lines. The pads are preferably placed at opposed ends of a conductive line to allow testing of the continuity of the entire conductive line. Extra material defects may be detected by electrically testing for connectivity between the conductive lines of the test structure. Missing material defects may be detected by testing for continuity of a conductive line.